1. Field of the Invention
The present invention is related to an integrated circuit implementing a method for removal of silicon carbide layers and in particular amorphous SiC of a substrate.
2. Description of Related Art
SiC (Silicon Carbide), particularly amorphous SiC, is known as a chemically very stable component. In semiconductor processing, many modules, defined as a set of subsequent basic steps, require the presence of a thin layer which remains substantially unaffected by the operation being performed, i.e. so-called semi-inert layers. Particularly, such a semi-inert layer can be used as a hard mask layer during dry etch, or as an etch stop layer during wet/dry etch, or as stopping layer for a Chemical-Mechanical polishing process (CMP) or for many other applications. For instance, these semi-inert layers can also be used as diffusion barrier layers. Due to it""s high chemical stability, the use of a SiC layer as a semi-inert layer may have benefits over other materials such as silicon dioxide and silicon nitride, especially for those applications where selectivity to the operation being performed is of high importance for successful implementation. In addition, SiC layers may be superior in terms of barrier properties. Document U.S. Pat. No. 5,818,071, which is incorporated by reference in its entirety, is related to interconnect structures incorporating a silicon carbide layer as a diffusion barrier layer particularly between a dielectric and a highly conductive metal layer with a resistivity less than about 2.5 microhm-centimetres. Document U.S. Pat. No. 5,818,071, which is incorporated by reference in its entirety, does not disclose the use of a silicon carbide layer as an etch stop layer and a diffusion barrier layer in pre-metal dielectric structures, particularly between a silicide layer and a dielectric. U.S. Pat. No. 5,818,071, which is incorporated by reference in its entirety, does not disclose how to pattern or to remove the silicon carbide layer selectively to the underlying layer, in casu a metal layer.
Although a silicon carbide layer is a very attractive layer to use in semiconductor processing and particularly in interconnect structures and dielectric structures, its high chemical stability can also be its biggest disadvantage. SiC suffers from the fact that it is very difficult (if not impossible at all) to remove and particularly to remove it selectively. Some examples of process flows where such removal is required are: the stopping layers in the CMP operations for definition of field area""s using the shallow trench isolation approach; and the use as etch stop layers for contact and via definition, where the process flow requires the selective removal of the etch stop layer at the bottom of the contact/via to obtain low contact/via resistance. Another example is also related to the use of SiC as a stopping layer in CMP applications. The cleaning after CMP usually relies on under-etching of the particles/residues. This requires that the surface from which particles and/or residues need to be removed can be etched isotropically in a very controlled way. However, due to the high chemical stability of SiC, particles and/or residues on top of the SiC layer can not be under-etched and therefore, cleaning becomes rather difficult.
Document EP-A-0845803, which is incorporated by reference in its entirety, discloses the removal of a surface portion of a crystalline SiC film. First, defects are introduced in the top layer, thereafter, the top layer is converted into a silicon oxide layer by a thermal oxidation treatment typically at a temperature of 1100xc2x0 C. This renders this process unsuited for use in interconnect structures and pre-metal dielectric (PMD) structures because active devices are already defined and therefore only limited thermal treatments can be applied, i.e. typically 600xc2x0 C. or below. Moreover, the silicide layers in the PMD structures, are also not compatible with temperatures above 650xc2x0 C., while most metal features in the interconnect structures are not compatible with temperatures typically above about 400xc2x0 C.
Aims of the Invention
It is an aim of the invention to remove exposed layers of a SiC layer by converting at least a major part of said SiC layer in silicon (di) oxide or silicon oxide based layers. Particularly this conversion is performed at low temperatures, preferably 600 C. or below, in an oxygen-containing plasma. Thereafter the converted part of said SiC layer is removed.
It is a further aim of the invention to provide a method for fabricating an interconnect structures, including PMD structures, using SiC as etch stop layer and/or diffusion barrier layer by using the aforementioned method for in-situ selective removal of exposed layers of the SiC layer.
It is still a further aim of the invention to provide an interconnect structure, particularly a PMD structure wherein a SiC layer can be used as an etch stop layer between a conductive layer and the surrounding dielectric.
This invention is about the selective removal of exposed layers of SiC layers which allows the use of this highly chemically stable material for a wide range of applications. At least for the purpose of this disclosure a carbide-silicon layer is an insulating layer being composed of at least Si and C, e.g., but not limited hereto, SiC, or at least Si, C and O, e.g. silicon oxycarbide, or at least Si, C and N, e.g. nitrided silicon carbide (SiNC) or at least Si, N, O and C, e.g. nitrided silicon oxycarbide (SiNOC), or at least Si, C and H e.g. amorphous hydrogenated silicon carbide (SiC: H), or at least Si, C, N and H, e.g. hydrogenated SiNC, or at least Si, 0, C, N and H, e.g. hydrogenated SiNOC. For the purpose of this disclosure, an oxide-silicon layer is a layer composed of at least Si and O, e.g. silicon (di) oxide, or of Si, O and a smaller fraction of C and/or a smaller fraction of N and/or a smaller fraction of H, for example silicon (di) oxide wherein the fraction of C and/or N and/or H smaller is than the fraction of O.
In an aspect of the invention, a method for removing at least partly an exposed part of a carbide-silicon layer formed on a substrate is disclosed comprising the steps of:
converting at least partly said exposed part of said carbide-silicon layer into an oxide-silicon layer by exposing said carbide-silicon layer to an oxygen containing plasma,
removing said oxide-silicon layer from said substrate.
Said exposed part can be, but is not limited hereto, an exposed part in an opening or can be at least an exposed part of a layer.
This method can be applied in-situ. The substrate can be, but is not limited hereto, a partly processed or a pristine wafer or slice of a semi-conductive material, like Si or Ga As or Ge, or an insulating material, e.g. a glass slice, or a conductive material. Said substrate can comprise a patterned conductive layer. Particularly, in case said substrate is a partly processed wafer or slice; at least a part of the active and/or passive devices can already be formed and/or at least a part of the structures interconnecting these devices can be formed.
For the purpose of this disclosure, plasma should be understood as a conventional plasma such as a reactive ion etch (RIE) plasma or a chemical vapour deposition (CVD) plasma, or a plasma afterglow. By exposing said carbide-silicon layer to an oxygen-containing plasma, energy is given to the oxygen containing species, such that carbide-silicon is at least partly converted into oxide-silicon. This energy can be e.g. thermal energy or kinetic energy, e.g. by the formation of ions.
In accordance with an exemplary embodiment of the present invention, a method as recited in the first aspect of this invention is disclosed, wherein said conversion step and said removal step are subsequently repeated for a number of times until said carbide-silicon layer is substantially removed.
In accordance with another exemplary embodiment of the present invention, the conversion from a part of the carbide-silicon layer to an oxide-silicon layer can be performed by exposing the carbide-silicon layer to an oxygen-containing reactive ion etch (RIE) plasma. Particularly, the substrate including the carbide-silicon layer can be introduced in a pressurized chamber of a plasma-etch tool. The pressure can be lower than 3 Torr and preferably between 1 mTorr and 1 Torr. The temperature in said chamber can be 300xc2x0 C. or below; or preferably below 100xc2x0 C. This temperature can also be in the range from xe2x88x9220xc2x0 C. to 100xc2x0 C. Preferably, said temperature is about room temperature. The energy of the RIE plasma can be between 1 eV and 500 eV, such that ionic species can be formed.
In accordance with another exemplary embodiment, the conversion from a part of the carbide-silicon layer to an oxide-silicon layer can be performed by exposing the carbide-silicon layer to an oxygen-containing CVD plasma. The substrate including the carbide-silicon layer can be introduced in a pressurized chamber of a chemical vapor deposition tool. The pressure can be, but is not limited hereto, higher than 5 Torr, e.g. 10 Torr. The temperature can be in the range between 250xc2x0 C. and 550xc2x0 C., preferably in the range between 350xc2x0 C. and 500xc2x0 C.
In accordance with yet another exemplary embodiment of the invention, the conversion from a part of the carbide-silicon layer to an oxide-silicon layer can be performed by exposing the carbide-silicon layer to an oxygen-containing plasma afterglow. Particularly, the substrate including the carbide-silicon layer can be introduced in a pressurized chamber of a plasma tool. Said plasma afterglow can be characterized, but is not limited hereto, by a pressure in the range from 0.02 Torr to 3 Torr, and in the range between 0.2 Torr and 1.5 Torr and preferably between 0.75 Torr and 1.25 Torr, e.g. about 0.85 Torr or about 1.1 Torr. The flow of the oxygen containing substance can be lower than 10000 Sccm and preferably, but not limited hereto, about 4000 Sccm.
The temperature in said chamber is preferably 600xc2x0 C. or below. This temperature can also be in the range from 100xc2x0 C. to 600xc2x0 C. and also in the range from 200xc2x0 C. to 400xc2x0 C. and also in the range from 200xc2x0 C. to 300xc2x0 C. This temperature is preferably, but not limited hereto, about 230xc2x0 C.
In another aspect of the invention, an integrated circuit on a substrate with at least one conductive layer being partly exposed is disclosed, said circuit comprising:
a conductive layer deposited on a semiconducting layer,
at least one dielectric layer having at least one opening extending through said dielectric layer to expose at least a part of said conductive layer,
a carbide-silicon layer being formed at least on said conductive layer and being positioned between said dielectric layer and said conductive layer adjacent to said exposed part of said conductive layer.
Said conductive layer can be a pure metal or a metal alloy of the group of metals consisting of Al, Cu, W, Pt, Ag, Ni, Au, Co, Ti, Ta; or a Si-containing or other semiconductor-containing layer such as, but not limited hereto, e.g. a silicide, a polysilicon or a silicon layer. Said semiconducting layer can be a silicon containing layer, a GaAs layer, a Ge layer or a SiGe layer. Said dielectric layer has preferably a dielectric constant of less than about 4.
In accordance with an exemplary embodiment the invention an integrated circuit comprising an interconnect structure on a substrate having a surface with at least one exposed Si-containing layer, particularly a PMD structure, is disclosed. This interconnect structure further comprises:
a conformal silicide layer on said exposed Si-containing layer;
at least one dielectric layer on said surface of said substrate having at least one opening, said opening extending through said dielectric layer to thereby define an exposed part of said silicide layer; and
a carbide-silicon layer being formed at least on said silicide layer and being positioned between said dielectric layer and said silicide layer adjacent to said exposed part of said silicide layer.
A silicide layer can be a compound comprising silicon and at least one of the group comprising Co, Ti, Ta, Co, Mb, Ni, Pt and W.
In yet a further aspect of the invention, a method for fabricating an integrated circuit on a substrate having a surface with at least one conductive layer on a semiconducting layer is disclosed. This conductive layer can be a pure metal or a metal alloy of the group of metals consisting of Al, Cu, W, Pt, Ag, Ni, Au, Co, Ti, Ta; or a Si-containing or other semiconductor-containing layer such as, but not limited hereto, e.g. a silicide, a polysilicon or a silicon layer.
This method comprises the steps of:
forming a carbide-silicon layer at least on said conductive layer;
depositing at least one dielectric layer on said surface and on said carbide-silicon layer;
forming at least one opening in said dielectric layer extending through said dielectric layer to thereby expose a part of said carbide-silicon layer formed on said conductive layer;
in-situ converting said exposed part of said carbide-silicon layer in said opening into a oxide-silicon layer by exposing said exposed part of said carbide-silicon layer in said opening to an oxygen-containing plasma; and
removing said oxide-silicon layer in said opening.
Said conversion step and said removal step can subsequently be repeated for a number of times until at least a part of said conductive layer is exposed.